Performance-Driven Routing with Multiple Sources

Existing routing problems for delay minimization consider the connection of a single source node to a number of sink nodes, with the objective of minimizing the delay from the source to all sinks, or a set of critical sinks. In this paper, we study the problem of routing nets with multiple sources, such as those found in signal busses. This new model assumes that each node in a net may be a source, a sink, or both. The objective is to optimize the routing topology to minimize the total weighted delay between all node pairs (or a subset of critical node pairs). We present a heuristic algorithm for the multiple-source performancedriven routing tree problem based on efficient construction of minimumdiameter minimum-cost Steiner trees. Experimental results on random nets with submicrometer CMOS IC and MCM technologies show an average of 12.6% and 21% reduction in the maximum interconnect delay, when compared with conventional minimum Steiner tree based topologies. Experimental results on multisource nets extracted from an Intel processor show as much as a 16.1% reduction in the maximum interconnect delay, when compared with conventional minimum Steiner tree based topologies. Index Terms— Interconnections, interconnect topology optimization, layout, minimum diameter routing tree, multisource routing tree, rectilinear arborescience, Steiner tree. Manuscript received May 8, 1995; revised April 29, 1996 and December 17, 1996. This work was supported in part by DARPA/ITO under Contract J-FBI-93-112, an NSF Young Investigator Award MIP9357582, and a grant from Intel Corporation. This paper was recommended by Associate Editor C.-K. Cheng. The authors are with the Computer Science Department, University of California, Los Angeles, CA 90024-1596 USA. Publisher Item Identifier S 0278-0070(97)05151-8. I. INTRODUCTION The competitive nature of the very large scale integration (VLSI) industry has created a strong demand for techniques to improve the performance of integrated circuits. Methods to increase speed, and to reduce area or power consumption, are of great interest. Scaling of device dimensions has resulted in changes to many fundamental design goals: where previously the bulk of system delay had been generated by the switching times of devices, it is now common that the interconnecting wires between devices accounts for the dominating portion of the delay. These changes have created new areas in need of optimization, and new measures by which we gauge solution quality. With smaller minimum feature size comes a reduction in transistor channel width and length, resulting in relatively constant transistor on resistance; the reduction in wire width, on the other hand, results in higher unit wire resistance [2]. As a result, the resistance ratio [8], defined to be the driver resistance divided by the unit length wire resistance, is reduced significantly. This shift produces a situation where the length of the path between a driver and sink can have comparable resistance to that of the transistor channel. Thus, changes to the interconnect length and topology can have a significant impact on delay. The result in [11] showed convincingly that interconnect topology optimization has a considerable effect on interconnect delay reduction when the resistance ratio is small. A number of optimized interconnect topologies have been proposed, including bounded-radius bounded-cost trees [9], AHHK trees [1], LAST trees [21], maximum performance trees [7], A-trees [11], low-delay trees [5], and IDW/CFD trees [18]. These methods consider both the traditional concern of low total wire length, and also the path length or Elmore delay between the source node and the timingcritical sink nodes. Although many of these methods effectively reduce the interconnect delay, all of them assume that there is a single source node driving one or more sink nodes and minimize the delay from the unique source to all sinks, or a set of critical sinks. In practice, many timing-critical nets may have multiple sources, each of them controlled by a tri-state gate and driving the net at a different time. Signal busses are instances of such nets. In these cases, the existing performance-driven routing algorithms for single source nets may perform poorly, as a topology optimized for one source may result in high interconnect delay when some other source becomes active. Fig. 1 presents a pair of four-node routing trees with the same wire length. The first routing tree, optimized for node has relatively high delay when node drives the net. The second routing tree provides a lower overall maximum delay when all four nodes might be sources or sinks. Delay times with respect to the driving nodes are shown in Table I. Note that the second routing tree, which minimizes the maximum linear delay, does not fall entirely on the Hanan grid [16]. For the single source model under Elmore delay, [4] showed that an optimal tree which minimizes the maximum delay to any sink may not be contained by the Hanan grid, but also observed that these cases were rare. For problems with multiple sources, a solution restricted to the Hanan grid may be far from the optimal solution, as shown in Fig. 1. Therefore, we cannot restrict our search for solutions to this grid. In this paper, we study the problem of routing nets with multiple sources. This new model assumes that each node in a net may be a source, a sink, or both. The objective is to optimize the routing 0278–0070/97$10.00  1997 IEEE IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 4, APRIL 1997 411 Fig. 1. An example of the impact of path length on delay. The first routing tree is optimized for node ! When " #%$ drives the net, however, performance suffers. The second routing tree provides a lower maximum delay when both &(' and )+* can drive the net. TABLE I TOPOLOGY , EFFECTS ON DELAY. FOR , A N ET WITH MUL . TIPLE SOURCES, , THE D / ELA 0 Y TO A GIVEN 1 SINK 1 D / EPENDS 0 ON W " HICH 2 N ODE , D / RIVES 3 THE N ET 0 topology 4 to minimize the total weighted delay between all node pairs, where 5 the weight between a node pair indicates the priority of delay minimization 6 between this pair of nodes. We present an algorithm for the 4 performance-driven multiple source routing tree problem based on construction 7 of minimum 8 diameter A-trees. Some preliminary results of 9 our work were presented in ISCAS ’95 [12]. II. PROBLEM : FORMULA ; TION Given < a set of points =?>A@CB D EGF HJILK K K MONQP(R on the Manhattan plane, S and a nonnegative weight TVUXWQY[ZO\ ]_^ as ` the weight between a each b pair of source c d and sink e f to indicate the timing criticality between a this pair of points, the performance-driven g multiple source r h outing tree (PD-MSRT) problem is defined as finding a Steiner tree i which 5 connects all points in j and ` minimizes the following two objectives: 9 • total weighted delay kmlonqpsr between a pairs of nodes t u and ` v w ; i.e., xzyo{q|~}€  ‚  ƒV„X… †[‡qˆ ‰_ŠŒ‹Ž+_’‘”“ •—–Q˜[™Oš ›_œ ;  • total tree length žsŸ’ ~¡£¢ defined ¤ as the sum of the lengths of each tree 4 edge. W ¥ e assume that the first objective has higher priority than the second ¦ one. For simplicity, one may assume that §© ̈—a «[¬’­(® ̄±°32 ́¶μ_·L ̧q1 i.e., noncritical pairs of points have weight zero, and critical pairs have o weight one. Values between 0 and 1 provide a greater degree of 9 freedom in “tuning” for performance optimization, although the heuristic o presented here can make only limited use of this. The delay ¤ between a pair of points, »”1⁄4_1⁄2q3⁄4+¿ À—Á Â[ÃÅÄ(Æ Ç£È may be estimated using É an appropriate model, such as the linear delay model (where delay ¤ is proportional to path length), the Elmore delay model [15], or 9 calculated using SPICE. Given < a point ÊQËÍÌÏÎÑÐ we 5 use ÒOÓÕÔ[ÖØ×%ÙOÚ to denote the Û and ` Ü coordinates 7 of point Ý ÞGß We will utilize an additional point à in some proofs, S and denote its location with áOâ ãåäçæ%è_éØê For any two points ë ì and í(îåï we define the distance ð ñ—ò óGô’õ(ö ÷ between them as their Manhattan distance, ø ùÕú ûŽü”ý+þçÿ Given < a tree we define the 4 distance between nodes and in as